This application relies for priority upon Korean Patent Application No. 2000-50419, filed on Aug. 29, 2000, the contents of which are herein incorporated by reference in their entirety.
1. Technical Field
The present invention generally relates to a shallow trench isolation type semiconductor device and a method of forming the same. More specifically, the present invention is directed to a shallow trench isolation type semiconductor device in which insulating layers differ in thickness according to regions, and a method of forming the same.
2. Discussion of Related Art
A common problem encountered in device isolation in a high-density semiconductor device is a bird's beak effect, which occurs due to a lateral growth of thermal silicon dioxide in the form of a bird's beak under a SiN4 protective layer. The bird's beak is undesirable since it takes up needed area and has electrical field effects that permit current leakage. A shallow trench isolation (STI) technique for device isolation has been widely used and avoids the problem of the bird's beak effect. However, to achieve superior device isolation results, the depth and width of a trench must be increased. Since it is desirable to have semiconductor devices having small footprints for higher integration, the depth must be increased while the width for insulation must be decreased. In a less than ideal scenario, a deep trench cannot be formed due to the decrease in the width.
When a high voltage is applied, the component at which a high voltage is applied must have a structure that is able to withstand the high voltage. Typically, a gate insulating layer formed at the part where the high voltage is applied is made thicker than the gate insulating layer formed at others.
FIG. 1 is an exemplary cross-sectional view showing the difference in thickness of a gate insulating layer at a low voltage part of cell and peripheral regions compared to a gate insulating layer at a high voltage part of the peripheral region. FIG. 1 also shows an exemplary formation of a self-aligned trench in each region of a flash memory device in which the gate insulating layers differ in thickness. At the peripheral region where the gate insulating layer 13 is thickly formed, a trench 17 for device isolation is shallowly formed, which increases the probability that insulation for device isolation will not be sufficient.
FIG. 1 includes gate insulating layers 11 and 13 which differ in thickness according to each region of a substrate 10. Conventionally, the thickness of the gate insulating layer 11 formed at a low voltage part of cell and peripheral regions is about 70 Å to about 80 Å and the thickness of the gate insulating layer 13 formed at a high voltage part of the peripheral region is about 250 Å to about 350 Å. A polysilicon layer 15 for forming a part of a self-aligned floating gate is stacked on the gate insulating layers 11 and 13. Based upon the STI technique, device isolation is then carried out. In other words, an etch-stop layer made of silicon nitride is deposited. Preferably, a high temperature oxide (HTO) layer is then deposited for patterning the etch-stop layer, and an anti-reflection coating (ARC) layer is additionally deposited.
Through photoresist coating, exposure using a device isolation mask pattern, and development, a trench pattern for device isolation is formed. Subsequently, upper layers are sequentially etched to be removed. A patterned upper layer can serve as an etching mask to a lower layer. Generally, the etch-stop layer is patterned and the photoresist pattern is removed by ashing and stripping techniques. The polysilicon layer 15, the gate insulating layers 11 and 13, and the substrate silicon layer 10 are etched to form a trench. In the etching process to form the trench, separately etching the gate insulating layer and the substrate causes problems due to shifting of the etching apparatus. Thus, the process is carried-out in one etching apparatus (i.e., “in-situ”). It takes a great deal of time to etch a gate insulating layer at a part where the gate insulating layer is thickly formed. With a conventional silicon oxide layer and silicon etchant for forming a trench, a depth difference (A) of about 180 Å to about 500 Å is observed in a substrate trench where the gate insulating layer is thickly formed. Naturally, the depth difference (A) varies according to the type of etchant used.
Preferably, after thinly stacking a sidewall oxide layer and a silicon nitride liner, the trench is filled with a CVD oxide layer. To complete the trench isolation layer 17, a chemical mechanical planarization (CMP) process for removing the stacked CVD oxide layer on a region except the trench, a wet etching process to remove an etch-stop layer made of silicon nitride, and a cleaning process are then performed. However, where the gate insulation layer is thickly formed, a thickness of the isolation layer 17 has a depth difference (A) as great as a depth of the trench. This is disadvantageous, since if the isolation layer 17 becomes thin at a transistor peripheral region to which a high voltage is applied, device isolation can be incomplete.
Therefore, a need exists for a shallow trench isolation type semiconductor device and a method of forming the same, which can complement a trench isolation layer whose thickness in a silicon substrate is not sufficient. A need also exists for a shallow trench isolation type semiconductor device and a method of forming the same which can complement incomplete device isolation caused by a trench isolation layer whose thickness in a silicon substrate is not sufficient in certain regions due to a thicker gate insulating layer. Additionally, a need exists for a shallow trench isolation type semiconductor device and a method of forming the same which can complement a device isolation layer whose thickness is not sufficient without causing an aligning problem.